Integrated circuits are often provided with protective integrated structures against electrical discharges of electrostatic origin which may hit an external pin of the integrated circuit.
The basic principle of operation of an electrostatic discharge (ESD) protective device consists in limiting to an established maximum tolerable value, dictated by the particular fabrication process, voltage spikes which may occur on the pins of the integrated circuit, in order to prevent breakdown of integrated structures which are connected to the respective pins, and which because of their intrinsic characteristics are often unable to tolerate voltage spikes greater than a certain amplitude. The amplitude of voltage spikes of an electrostatic origin may easily reach several KV with a maximum energy associated therewith on the order of several mjoule, e.g. according to the so-called "Human Body Model". In view of the fact that the rise time of these spikes is typically a few nanoseconds (ns), the reaction time of the protection structure must be extremely fast. Commonly the integrated structures used for implementing an ESD protection are constituted by Zener diodes, SCR, and lateral NPN structures with a resistive connection between base and emitter. A prior art integrated structure of this latter type, as depicted in FIG. 1, has the configuration of a lateral NPN transistor wherein its base region is connected to its emitter region through a resistive path. The structure may be considered a diode constituted by the base/collector junction, which exhibits a voltage/current characteristic having a well defined zone showing a negative slope in the first quadrant.
Other equivalent electrical schemes of the prior art integrated structure of FIG. 1 are shown in FIGS. 2A and 2B for simplicity's sake or the prior art integrated structure of FIG. 1 may be symbolically indicated by means of a diode symbol inscribed in a circle together with an asterisk, as depicted in FIG. 2C.
Commonly in literature, this prior art discharge structure is referred to simply as "lateral NPN", with the understanding that the NPN structure includes a resistive connection between the base and emitter regions, when configured for use as an ESD protection device.
In addition, some pins of integrated circuits (e.g. an input pin) must be capable of operating with negative voltages with respect to ground (i.e., below ground), and/or with voltages higher than the supply voltage, as it is well known to a person skilled in the art. An ESD protection device may be implemented also for these pins; a prior art such device is symbolically shown in FIG. 3. In such prior art devices, the ESD protection device is implemented by utilizing two Zener diodes, Z1 and Z2, or two lateral NPNs with a resistive connection between base and emitter, connected in series and in opposition with each other between the (input) pin to be protected and a substrate of the integrated circuit connected to ground.
This type of prior art integrated protection structure has several drawbacks tied to the triggering of an intrinsic parasitic transistor which makes the structure unusable in integrated circuits wherein a very small current absorption of the ESD protection structure must be ensured; for example, in the case of an input pin of an operational amplifier. FIGS. 4 and 5 show schematically a prior art integrated protection structure realized in an integrated circuit having typical junction-isolation architecture and comprising a p-type semiconducting substrate and an n-type epitaxial layer, wherein the various devices are formed within regions of the n- type epitaxial layer laterally defined by p+ isolation diffusions. Both in FIG. 4 and in FIG. 5, a PNP parasitic transistor (PNPparas.), is intrinsic to the integrated protection structure Z2.
In this case, the base current of the parasitic transistor is constituted by the leakage current (Ileak) of the diffusions which realize the two Zener diodes, Z1 and Z2, beside the intrinsic leakage current of the Z2 diode and the total current drawn by the ESD protection structure through the protected pin. This total current is given by the following relation: EQU I.sub.tot =I.sub.leaktot .times.G
where G is the current gain of the parasitic transistor, which is intrinsic to the integrated ESD protection structure.
As a consequence the current which is drawn (or injected) through the relative pin of the integrated circuit, the current represents an intrinsic leakage current amplified by the parasitic transistor and, therefore, may reach untolerable levels for many applications. A parasitic PNP transistor is also present also within the integrated structure of a lateral NPN and is provided with a resistive connection between base and emitter, which is usable in place of a Zener structure as a discharge element, as symbolically shown in FIG. 1.